1. Technical Field of the Invention
The present invention relates to integrated circuits, and in particular electrically programmable and erasable non-volatile type memory devices. More particularly, the invention relates to a non-volatile memory device and a method of programming such a device.
2. Description of Related Art
A non-volatile memory device conventionally comprises a set of memory points arranged in the form of a network of memory cells used to store information in the form of a set of data words.
The structure of a non-volatile type memory point is well known to those skilled in the art. For this, reference can be made to U.S. Pat. No. 5,761,121, the disclosure of which is hereby incorporated by reference, which gives a description of this for a PMOS structure.
More specifically, a non-volatile memory cell is based on the use of a floating-gate transistor associated with a control gate which is used to control the transfer of charge carriers to the floating gate to be stored there permanently.
FIG. 1 shows the structure of a conventional non-volatile memory cell with floating-gate transistor. As can be seen in this figure, the floating gate FG of a cell C is made of polysilicon on top of a channel region which extends between two source S and drain D doped regions, referenced 2 and 3, located in a silicon substrate S, in this case of type P, with an interposed gate oxide layer 4. The control gate CG is formed on top of the floating gate FG with an interposed insulating film 5. Spacers 6 and 7 are provided either side of the floating gate and of the control gate.
As can be seen, the control gate is coupled capacitively to the floating gate. As for the floating gate, it is insulated such that the charges transferred to it remain stored until a high voltage is applied to the source, the drain and the substrate of the transistor and a much weaker voltage is applied to the control gate, which causes the appearance of a strong reversed electrical field followed by a draining of the electrons stored in the gate, passing through the gate oxide.
To program the memory cell, it is possible, for example, to perform a Fowler-Nordheim type programming, that is, to apply a strong electrical field to the control gate to lower the energy barriers and allow electrons to pass to the floating gate. With the application of the high electrical field to the floating gate, said floating gate is raised to a high potential. A voltage equal to 0 volts is then applied to a contact point of an active area of the substrate in which electrons are stored. Because of this, a strong electrical field is created which attracts the electrons from the active area to the floating gate through the gate oxide 4.
Non-volatile memory devices are designed for more or less permanent data storage. It has therefore been specified that the non-volatile memory cells must have data retention capacities such that they need to be able to remain in a programmed state for a time that can range up to several years.
However, the data retention capacities of the memory cells are linked to the thickness of the gate oxide used to insulate the floating gate. Thus, to be able to remain in the programmed state for the required time, the memory cells need to have a gate oxide layer at least 85 Angstroms thick. Below this value, the electrons stored in the floating gate are likely to pass through the polysilicon/oxide/silicon barriers to migrate towards the substrate. Such a phenomenon is generally called “tunneling”.
Thus, if the thickness of the gate oxide is insufficient, there is a high probability that direct tunneling phenomena will appear, which is accompanied by a resulting loss of charges within the floating gate. This loss of charges is then likely to lead to a corruption of a stored binary value.
In view of the above, there is a need in the art to provide a non-volatile memory device in which the data retention capacity is enhanced.
There is also a need to allow for the creation of a non-volatile memory device with a thinner oxide layer.
There is still further a need to allow for the creation of a non-volatile memory device having an enhanced data retention with a gate oxide thickness that can range up to 50 Angstroms and this using a standard CMOS technology.